// Copyright (C) 1953-2022 NUDT
// Verilog module name - ptp_rx
// Version: V4.1.0.20221205
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         receive ptp packet
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module ptp_rx #(parameter ptp_rx_offset = 16'd192)
(
    i_clk  ,
    i_rst_n,

    i_slave_port  ,    
    
    iv_data  ,
    i_data_wr,
    
    ov_data       ,
    o_data_wr     ,
    ov_eth_type        ,
    ov_ptp_messagetype , 
	o_diagest_wr,
    
    o_osm_req_rx_pulse       ,
    o_osm_resp_rx_pulse      ,
	o_osm_sync_rx_pulse
   
);
// I/O
// clk & rst
input                   i_clk  ;
input                   i_rst_n;
//input
input                   i_slave_port  ;   

input       [7:0]       iv_data  ;
//input       [8:0]       iv_data  ;
input                   i_data_wr;
//output
output      [8:0]       ov_data          ;
output                  o_data_wr        ;
output      [15:0]      ov_eth_type         ;
output      [3:0]       ov_ptp_messagetype  ;
output                  o_diagest_wr        ;
           
output                  o_osm_req_rx_pulse        ;
output                  o_osm_resp_rx_pulse       ;
output                  o_osm_sync_rx_pulse       ;

wire        [8:0]       wv_data_htd2fifo          ;
wire                    w_data_wr_htd2fifo        ;

head_and_tail_add head_and_tail_add_inst
(
    .i_clk           (i_clk             ),
    .i_rst_n         (i_rst_n           ),

    .i_data_wr       (i_data_wr         ),
    .iv_data         (iv_data           ),

    .ov_data         (wv_data_htd2fifo  ),
    .o_data_wr       (w_data_wr_htd2fifo)
);

ptp_process  #(.ptp_rx_offset(ptp_rx_offset))ptp_process_inst
(
    .i_clk                      (i_clk               ),
    .i_rst_n                    (i_rst_n             ),
                                                      
    .i_slave_port               (i_slave_port        ),                                                      
                                                     
    .iv_data                    (wv_data_htd2fifo    ),
	.i_data_wr                  (w_data_wr_htd2fifo  ),
	//.iv_data                    (iv_data    ),
    //.i_data_wr                  (i_data_wr  ),
                                                     
    .ov_data                    (ov_data             ),
    .o_data_wr                  (o_data_wr           ),
    .ov_eth_type                (ov_eth_type         ),
    .ov_ptp_messagetype         (ov_ptp_messagetype  ),    
    //.ov_local_count_rx          (ov_local_count_rx   ),
    .o_diagest_wr               (o_diagest_wr        ),
    
    .o_osm_req_rx_pulse         (o_osm_req_rx_pulse  ),
    .o_osm_resp_rx_pulse        (o_osm_resp_rx_pulse ),
    .o_osm_sync_rx_pulse		(o_osm_sync_rx_pulse )
    //.o_sync_pulse_portrx        (o_sync_pulse_portrx)

); 
endmodule
